Embedded dynamic random access memories (eDRAMs) are employed in devices such as power processors and application specific integrated circuits (ASICs). Arrays of such memories are fabricated with operatively associated field effect transistors (FETs) using CMOS technology. Various approaches have been proposed for reducing parasitic leakage in devices incorporating eDRAMs. For example, some silicon-based devices include thick oxide linings or collars on the top portions of the trench capacitors to suppress parasitic leakage.
A trench capacitor is a three dimensional device formed by etching a trench into a semiconductor substrate. A node dielectric layer is formed on the inner walls of the trench. The trench is then filled with an electrically conductive material such as metal or highly doped polycrystalline silicon. N-type polysilicon within the trench can function as one electrode of the trench capacitor while an n-doped region surrounding the lower portion of the trench functions as the second electrode thereof. A transistor can be formed above and in electrical communication with the trench capacitor.
III-V compounds offer a number of advantages over silicon with respect to the operation of semiconductor devices. Compound III-V field effect transistors are among the devices that have benefitted from III-V CMOS technology.